1. Field of the Invention
The present invention relates to a clock generation circuit for generating a clock signal of a desired frequency band.
2. Description of the Related Art
As a circuit for generating a plurality of different frequencies, for example, there is known a circuit using a phase locked loop (PLL) circuit etc. to generate a frequency clock of the least common multiple thereof at first and dividing the same by a suitable ratio so as to generate a desired frequency clock.
For example, a 400 MHz clock is required for data-strobe coding in the case of a serial interface IEEE (Institute of Electrical and Electronic Engineers) 1394, particularly for 400 Mbp communication in a system wherein the cable is a long 4.5 m.
In addition to this, a clock of 500 MHz (400xc3x975/4 or xc3x9710/8) is required when increasing the length of a communication cable, for example 100 m, by changing a bit coding format to a 4B/5B system of communicating by changing 4 bits of data to 5 bits of symbols or to a 8B/10B system of communicating by changing 8 bits of data to 10 bits of symbols (work for standardization is actually underway as P1394B in the IEEE).
In a circuit of the related art, a clock having the least common multiple frequency of 2 GHz is generated and the 2 GHz clock is divided by 5 and 4 to generate a 400 MHz clock and a 500 MHz clock, respectively, in this case.
Note that the 4B/5B system and 8B/10B system are generally used in serial communication for the Ethernet or a fiber channel. Thus, the bit rate becomes 5/4 times the data rate.
On the other hand, in the data-strobe system, since data and a strobe (XOR of the data and the clock) are sent separately, the bit rate on a cable becomes the same as the data rate.
However, realization of a circuit for generating a 2 GHz clock is extremely difficult in a device like a 0.4 xcexcm CMOS.
Therefore, it becomes necessary to provide a separate PLL circuit for the 400 MHz and 500 MHz clock. However, this gives rise to the disadvantages of interference between the PLL circuits, an increase of power consumption, and an increase of a layout area due to the two PLL circuits.
An object of the present invention is to provide a clock generation circuit capable of obtaining a clock output of a desired frequency without causing an increase of power consumption and a chip area.
To attain the above object, according to a first aspect of the present invention, there is provided a clock generation circuit, comprising a multiphase clock generation circuit for generating multiphase clocks of a predetermined frequency, pulse generation circuits for generating a plurality of non-overlap pulses by using at least a part of the multiphase clocks of the multiphase clock generation circuit, and a combining circuit for combining a plurality of non-overlap pulses of the pulse generation circuits to generate a clock having a different frequency from that of the multiphase clocks.
According to a second aspect of the present invention, there is provided a clock generation circuit, comprising a multiphase clock generation circuit having a generation portion for generating reference multiphase clocks having a predetermined frequencies f0, a frequency divider for dividing by a dividing ratio M a frequency of one clock among the reference multiphase clocks of the generation portion, and a shifter for shifting a dividing signal of the frequency divider by a reference multiphase clocks; pulse generation circuits for generating a plurality of non-overlap pulses by using at least a part of the multiphase clocks output by the multiphase clock generation circuit; and a combining circuit for combining a plurality of non-overlap pulses by the pulse generation circuits to compose a clock having a different frequency fout from that of the reference multiphase clocks.
The dividing ratio M of the frequency divider of the multiphase clock generation circuit is preferably set to be value giving a clock equal to the least common multiple of the original frequency f0 and the period sought; the shifter obtains a multiphase clock by shifting by the number of stages required by the original reference multiphase clock having a half phase difference of a period of a frequency fout to be obtained in the combining circuit in that order; and the combining circuit generates a clock satisfying fout=(f0/M)xc2x7(N/2).
The multiphase clock generation circuit preferably comprises a phase synchronization circuit including a phase comparison means for comparing a reference signal with an internal signal and outputting a control signal in accordance with a comparison result and an oscillator, including a basic ring oscillator comprised of a plurality of differential delay circuits adjusted in delay time in accordance with at least the control signal and connected in a ring, generating a multiphase clock based on outputs of a plurality of differential delay circuits.
Alternatively the multiphase clock generation circuit comprises a phase synchronization circuit including a phase comparison means for comparing a reference signal with an internal signal and outputting a control signal in accordance with a comparison result and an oscillator, including a basic ring oscillator comprising an odd number of inverted delay circuits adjusted in delay time in accordance with at least with the control signal and connected in a ring, generating a multiphase clock by dividing outputs of the ring oscillator.
Each of the pulse generation circuits preferably comprises a generation means for generating a non-overlap pulse by being set at a clock edge and reset at another clock edge among the multiphase clocks of the multiphase clock generation circuit.
The generation means preferably comprises an asynchronous reset type flip-flop or an RS-type latch circuit.
The combining circuit preferably comprises an OR circuit.
The OR circuit is comprised of a wired OR circuit having a normally-on load.
That is, according to the present invention, multiphase clocks of a predetermined frequency are generated in the multiphase clock generation circuit and output to the pulse generation circuits.
In the pulse generation circuits, a plurality of non-overlap pulses are generated in the multiphase clock generation circuit by using at least a part of the multiphase clocks of the multiphase clock generation circuit and output to the combining circuit.
In the combining circuit, the plurality of non-overlap pulses of the pulse generation circuits are combined by an OR operation.
As a result, a clock having a different frequency from that of the multiphase clocks is generated.
Alternatively, according to the present invention, in the multiphase clock generation circuit, reference multiphase clocks having a frequency of f0 are generated in a generation portion. One clock among the reference multiphase clocks of the generation portion is supplied to the frequency divider. The clock is divided by a dividing ratio M at the frequency divider. Note that the dividing ratio M is set to a value giving a clock equal to the least common multiple of for example the original frequency f0 and the period sought.
A dividing signal of the frequency divider is shifted by a shifter for the number of stages required by the original reference multiphase clock having for example half a phase difference of a cycle of the frequency fout to be obtained in the combining circuit in that order.
As a result, multiphase clocks having N number of phases are output to the pulse generation circuits.
In the pulse generation circuits, a plurality of non-overlap pulses are generated by using at least a part of the multiphase clocks of the multiphase clock generation circuit and output to the combining circuit.
In the combining circuit, the plurality of non-overlap pulses by the pulse generation circuits are combined by an OR operation.
As a result, a clock having a different frequency fout=(f0/M)xc2x7(N/2) from that of the multiphase clocks is generated.